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2009 Microchip Technology Inc.

DS39636D-page 161

PIC18F2X1X/4X1X

16.3.8

OPERATION IN POWER-MANAGED

MODES

In SPI Master mode, module clocks may be operating

at a different speed than when in full power mode. In

the case of the Sleep mode, all clocks are halted.

In Idle modes, a clock is provided to the peripherals.

That clock should be from the primary clock source, the

secondary clock (Timer1 oscillator at 32.768 kHz) or

the INTOSC source. See Section 2.7 “Clock Sources

and Oscillator Switching” for additional information.

In most cases, the speed that the master clocks SPI

data is not important; however, this should be

evaluated for each system.

If MSSP interrupts are enabled, they can wake the

controller from Sleep mode, or one of the Idle modes,

when the master completes sending data. If an exit

from Sleep or Idle mode is not desired, MSSP

interrupts should be disabled.

If the Sleep mode is selected, all module clocks are

halted and the transmission/reception will remain in

that state until the devices wakes. After the device

returns to Run mode, the module will resume

transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

allows the device to be placed in any power-managed

mode and data to be shifted into the SPI Transmit/

Receive Shift register. When all 8 bits have been

received, the MSSP interrupt flag bit will be set and if

enabled, will wake the device.

16.3.9

EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

16.3.10

BUS MODE COMPATIBILITY

Table 16-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

TABLE 16-1:

SPI BUS MODES

There is also an SMP bit which controls when the data

is sampled.

TABLE 16-2:

REGISTERS ASSOCIATED WITH SPI OPERATION

Standard SPI Mode

Terminology

Control Bits State

CKP

CKE

0, 0

0, 1

1, 0

1, 1

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

PIE1

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

IPR1

PSPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

TRISA

TRISA7(2) TRISA6(2) PORTA Data Direction Control Register

TRISC

PORTC Data Direction Control Register

SSPBUF

SSP Receive Buffer/Transmit Register

SSPCON1

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

SSPSTAT

SMP

CKE

D/A

R/W

Legend: Shaded cells are not used by the MSSP in SPI mode.

Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’.

2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary

oscillator modes. When disabled, these bits read as ‘0’.

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